1. Field of the Invention
The present invention generally relates to compound-semiconductor devices and, more particularly, to a field-effect compound-semiconductor device in which a gate leakage current is suppressed.
2. Description of the Related Art
Compound-semiconductor devices are semiconductor devices that use a compound-semiconductor material for the active part of the device. Due to the characteristically very small effective mass of carriers in such a compound-semiconductor material, compound-semiconductor devices are used extensively for high speed applications. Such a high speed compound-semiconductor device includes HEMT and MESFET as a representative device, wherein an HEMT or an MESFET is used extensively for high-frequency applications.
In a field-effect compound-semiconductor device for such a high-frequency application, it is desirable to reduce a source resistance thereof as much as possible.
In order to reduce the source resistance of a field-effect compound-semiconductor device, it is desirable to reduce the distance between a source region and a gate electrode as much as possible. However, such a semiconductor device having a reduced source-gate distance tends to show a problem of increased leakage of the current flowing through a cap layer to the gate electrode.
FIG. 1 shows the construction of a typical conventional compound-semiconductor FET (field-effect transistor) 10.
Referring to FIG. 1, the FET 10 is a so-called doped channel transistor constructed on a semi-insulating compound-semiconductor substrate 11, and includes a channel layer epitaxially formed on the substrate 11 by an epitaxial process such as an MOVPE process. On the channel layer 12, there is provided a barrier layer 13 that forms a potential barrier with respect to the channel layer 12 for confining carriers in the channel layer 12, and a spacer layer 14 is formed further on the barrier layer 13 with a thickness adjusted such that the FET 10 has a desired threshold voltage. Further, an etching stopper layer 15 is formed on the spacer layer 14, and a cap layer 16 is provided further on the spacer layer 15.
The cap layer 16 is covered by an insulation film 17, and the insulation film 17 is formed with an opening 16A that penetrates through the cap layer 16, such that a top surface of the etching stopper layer 15 is exposed at the bottom of the opening 16A. It should be noted that the opening 16A is formed in correspondence to a channel region of the FET 10.
On the insulation film 17, there is provided a gate electrode 18 such that the gate electrode 18 fills the opening 16A and achieves direct contact with the etching stopper layer 15, and a pair of N.sup.+ -type diffusion regions 19A and 19B are formed at both lateral sides of the gate electrode 18, such that the diffusion regions 19A and 19B penetrate through the layers 16-12 and reach the substrate 11. Further, source and drain electrodes 20A and 20B are formed on the cap layer 16 in ohmic contact with the diffusion regions 19A and 19B, respectively.
In the doped channel transistor of FIG. 1, the problem of penetration of a surface depletion layer into the channel layer 12, and resultant repulsion of the carriers therefrom, is successfully avoided. Further, the depth of the opening 16A, in other words, the distance between the channel layer 12 and the gate electrode 18 filling the opening 16A, is set as desired, by providing the etching stopper layer 15. In order to avoid the leakage of the source current to the gate electrode 18, the cap layer 16 is formed of an undoped compound semiconductor material.
In such a doped channel transistor, there inevitably arises a problem in that a substantial gate leakage current flows when the distance between the source region 19A and the gate region 18 is reduced for minimizing the source resistance, particularly when a high gate voltage is applied to the gate electrode 18 for inducing carriers in the channel layer 12. This problem occurs even when the cap layer 16 is formed of a high-resistance undoped compound-semiconductor material.
A similar problem occurs also in a doped channel FET 10' shown in FIG. 2 in which the source and drain electrodes 20A and 20B are disposed at both lateral sides of the cap layer 16 for reducing the distance between the channel layer 12 and the ohmic electrode 20A or 20B.
Summarizing above, conventional compound-semiconductor FETs have suffered from the problem of gate leakage current. In other words, conventional compound-semiconductor FETs could not reduce the source-gate distance as desired because of the gate leakage current and have suffered from the problem of reduced operational speed caused by the source resistance.